Meta Iris's process node is heavily over-speculated. As of July 31, 2026, reporting says Iris will be built by TSMC with Broadcom design support — but nanometer node, power, and HBM are not reliably confirmed. This guide separates known partners from unverified specs.
Readers searching for "how many nanometers" or "TSMC foundry" often want a full spec sheet — but announcing partners is not the same as publishing specs. Meta's Broadcom partnership and reported TSMC manufacturing are citable facts; the actual process node remains a directional inference at best.
1Has Iris's Process Node Been Publicly Confirmed?
As of this writing, no reliable public source confirms Iris's specific process node. A July 2026 Reuters report says Iris will be manufactured by TSMC with Broadcom assisting on design — without disclosing 3nm, 5nm, or any other node. Meta's April 2026 Broadcom partnership expansion and March 2026 chiplet roadmap describe architecture direction and supply-chain roles, not full Iris hardware specs.
⚠️ Boundary check: "Manufactured by TSMC" identifies the foundry — it does not confirm a nanometer node. Supply-chain rumors turned into spec tables are the most common distortion on this topic.
Broadcom design collaboration
Power draw & core count
Low-precision & interconnect
2What Does TSMC Manufacturing Tell Us — and What Doesn't It?
Choosing TSMC suggests Iris may leverage advanced process lines, CoWoS-class packaging, and AI accelerator foundry experience — supporting more predictable scale deployment. But the foundry choice does not automatically imply a specific node, per-die power ceiling, or per-card memory capacity.
💡 Key focus: Scale deployment may depend more on packaging capacity, HBM supply, and rack interconnect than a single nanometer label.
3What Might Broadcom Bring to the Design Partnership?
Broadcom's role is custom chip design collaboration — not foundry manufacturing. Its datacenter networking, SerDes, and ASIC delivery experience may shape Iris's interconnect and system integration, supporting whether Iris can scale across recommendation, ads, and generative AI workloads. Transistor counts and peak compute numbers remain unknown.
| Information Type | Current Status | How to Read It |
|---|---|---|
| Foundry | TSMC (media reports) | Manufacturing & packaging capability expected |
| Design partner | Broadcom (official expanded partnership) | Custom ASIC & interconnect expertise |
| Process node | Not publicly confirmed | Do not cite unverified "nm" claims |
| MTIA 300–500 metrics | Partially disclosed directionally | Not equivalent to full Iris specs |
4What Can We Infer from the MTIA Roadmap?
Meta's MTIA path emphasizes modular chiplets, short iteration cycles, native PyTorch support, and low-precision inference types. MTIA 300–500 metrics provide context but are not confirmed Iris specs.
- Modular chiplets — May split compute and memory by workload; die count and bandwidth not yet confirmed.
- HBM — Inference workloads need high bandwidth; Iris may focus on HBM stacking, but capacity figures await disclosure.
- Low precision & PyTorch — FP8/INT8 paths may boost efficiency; a reasonable inference, not confirmed Iris parameters.
- Rack-level interconnect — Scale deployment needs multi-card networking; protocols and scale not yet public.
5Which Specs Should Not Be Stated as Confirmed?
Without official Meta or Hot Chips / ISCA disclosure, do not state as fixed: process node, TDP, peak FLOPS, HBM capacity, pricing, or production timelines. Use three tiers — known (foundry, design partner, MTIA direction), inferable (chiplets, HBM, low precision), and unknown (node, power, compute, price) — with language like "may" and "not yet confirmed."
6How to Verify Going Forward
When might Iris's process node get a reliable answer?
Watch Meta's engineering blog, academic papers, and Hot Chips / ISCA materials. Only upgrade to "known" after Reuters or Bloomberg second-confirm disclosures.
Does TSMC manufacturing guarantee the most advanced node?
Not necessarily. Foundries offer multiple nodes; products trade off performance, cost, and capacity. "TSMC" does not mean "latest nanometer node."
Is Broadcom the foundry?
No. Broadcom handles design collaboration; TSMC manufactures wafers. Do not conflate the two roles.
As of July 31, 2026, Iris's foundry and design partners are reported, but the process node has no reliable public confirmation. TSMC points to fabrication capability; Broadcom signals ASIC and interconnect expertise. Chiplets, HBM, and low precision are reasonable focus areas — not a confirmed spec table.
- 1Separate confirmed partners from unconfirmed process node
- 2Infer from MTIA roadmap; don't equate MTIA 300–500 metrics with Iris specs
- 3Track Meta disclosures and authoritative media — avoid fabricated spec stacking
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